1. Field of the Invention
This invention relates to a semiconductor device and its manufacturing method, specifically to a MOS transistor having a salicide (self aligned silicide) structure and its manufacturing method.
2. Description of the Related Art
A silicide structure as well as a salicide structure has been used to reduce gate resistance and source-drain resistance of a MOS transistor in order to enhance speed of the MOS transistor. FIG. 6 shows a cross-sectional structure of such a MOS transistor.
A gate electrode 52 is formed on an N-type silicon substrate 50 through a gate insulation film 51. A sidewall spacer insulation film 53 is formed on a sidewall of the gate electrode 52. A source layer 54 made of a P−-type diffusion layer 54a and a P+-type diffusion layer 54b and a drain layer 55 made of a P−-type diffusion layer 55a and a P+-type diffusion layer 55b are formed.
Titanium silicide (TiSix) layers 56a, 56b and 56c are formed on the gate electrode 52 and the P+-type diffusion layers 54b and 55b, respectively.
FIG. 7 shows a cross-sectional structure of a MOS transistor having another silicide structure. This MOS transistor is called a medium voltage MOS transistor which has a source withstand voltage and a drain withstand voltage of about 10V. The medium voltage MOS transistor is integrated on the same silicon substrate as the MOS transistor shown in FIG. 6.
A gate electrode 62 is formed on the N-type silicon substrate 50 through a gate insulation film 61, as shown in FIG. 7. A sidewall spacer insulation film 63 is formed on a sidewall of the gate electrode 62. A source layer 64 made of a P−-type diffusion layer 64a and a P+-type diffusion layer 64b, and a drain layer 65 made of a P−-type diffusion layer 65a and a P+-type diffusion layer 65b are formed.
The P+-type diffusion layers 64b and 65b are located away from the gate electrode 62 and the sidewall spacer insulation film 63, while the P−-type diffusion layers 64a and 65a are located adjacent the gate electrode 62. This structure relaxes electric field concentration in the source layer and the drain layer and provides a higher withstand voltage than the transistor structure shown in FIG. 6.
A titanium silicide layer 66a is formed on the gate electrode 62, a titanium silicide layer 66b is formed on the P−-type diffusion layer 64a and the P+-type diffusion layer 64b, and a titanium silicide layer 66c is formed on the P−-type diffusion layer 65a and the P+-type diffusion layer 65b. 
Further description on a MOS transistor having a silicide structure is found, for example, in Japanese Patent Application Publication No. 2002-353330.
Since the P+-type diffusion layers 64b and 65b are located away from the gate electrode 62 in the structure of the MOS transistor shown in FIG. 7, the P−-type diffusion layers 64a and 65a are exposed on the surface of the N-type silicon substrate 50. When titanium silicide is formed in this manner, titanium silicide layers 66b and 66c are formed on the P−-type diffusion layers 64a and 65a also. Since titanium absorbs P-type impurities (boron, for example) in the P−-type diffusion layers 64a and 65a during silicide reaction, junction depth of the diffusion layers is reduced to cause junction leakage.